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RM0008
11.12.15 ADC register map
The following table summarizes the ADC registers.
Analog-to-digital converter (ADC)
Table 67.
ADC register map and reset values
Offset
Register
0x00
ADC_SR
Reserved
Reset value
0
0
0
0
0
0x04
ADC_CR1
Reserved
DUALMOD
[3:0]
DISC
NUM [2:0]
AWDCH[4:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x08
ADC_CR2
Reserved
EXTSEL
[2:0]
JEXTSEL
[2:0]
Reserved
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0C
ADC_SMPR1
Sample time bits SMPx_x
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x10
ADC_SMPR2
Sample time bits SMPx_x
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x14
ADC_JOFR1
Reserved
JOFFSET1[11:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0x18
ADC_JOFR2
Reserved
JOFFSET2[11:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0x1C
ADC_JOFR3
Reserved
JOFFSET3[11:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0x20
ADC_JOFR4
Reserved
JOFFSET4[11:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0x24
ADC_HTR
Reserved
HT[11:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0x28
ADC_LTR
Reserved
LT[11:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0x2C
ADC_SQR1
Reserved
L[3:0]
Regular channel sequence SQx_x bits
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x30
ADC_SQR2
Regular channel sequence SQx_x bits
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x34
ADC_SQR3
Regular channel sequence SQx_x bits
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x38
ADC_JSQR
Reserved
JL[1:0]
Injected channel sequence JSQx_x bits
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Doc ID 13902 Rev 9
231/995
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